S100 Computers - 80486 CPU Board

An S-100 80486 CPU Board.
Baby 80486 CPU Board

Full Size 80486 CPU Board

I am not aware of there ever being manufactured an 80486 CPU board for the S100 bus. This was a pity because one unique feature of the 80486 is that it can "on the fly" talk to a data bus in single or multiple 8, 16 or 32 bit wide data bus modes as determined by the status of two input pins. This actually makes interfacing the chip to older 8 bit S100 boards easier than for an 80386, 80286 or 8086 CPU which do not have this 8 bit option.

Please note some of the topics discussed here are fairly complex. You should first read the complete entry for our 80386 CPU board before reading this section.

At first glance when you compare this chip to the 80386 CPU it might appear that splicing in an 80486 to our 80386 board would be simple. This in fact is not the case. The problem is that the 80486 delivers the data on one, two or four of its 8 bit bidirectional data lines differently depending on the desired address of the data and the data width. In contrast the 80386 always delivers 16 bit data (only on the lower 16 bit data lines). It cannot covert 16 or 32 bit data to sequential back to back 8 bit packages. Put another way, if the 80486 sends a 32 bit dword to RAM starting at 0H over an 8 bit bus, the first 8 bits will be on data lines 0-7, RAM byte 1 will have to receive data from the CPUs data lines 8-15. RAM byte 2 will get data from its data lines 16-23, and RAM byte 3 will get data from its data lines 24-31. This powerful feature requires careful redirection of the CPU's data lines all the time, particularly if you are sending data to the S100 bus unidirectional 8 bit data IN & OUT lines. There is simply no way to get normal enough 74LSxx chips on a single S100 board to handle this. This board as we shall see, utilizes an Atmel 1508 CPLD that is programed to condense multiple 74LSxx chips into a single chip. The complete source code to program each chip is provide below.

The good news is, the clock requirements for the 80486 circuit is now only a single clock -- as opposed to the dual clock signals of the 80386. This greatly simplifies the switching of the CPU low clock frequency for S100 bus access and the high "over the top bus" (OTT bus) speed access used with one or more daughter RAM boards. Unlike the AMD 80386's however there is a minimal 8MHz clock speed requirement for this CPU. The AMD (and later Intel) 80386 CPU's could downgrade the clock all the way to zero.

The second piece of good news is that because the 80486 can directly access data via an 8 bit data path it is now possible to place a single chip EPROM/EEPROM monitor directly on the board. With the 4GB address range of the CPU we will not get ourselves boxed in, we will go with a large size 2M X 8 EPROM using part or all of it as required.

Again because of space requirements there are some other minor differences from our 80386 and earlier 8066 and 80286 boards. The board can be configured as a IEEE-696 bus master or slave. Because all the master/slave S100 bus handshake signals are processed in the CPLD it can also be configured down one further level as a slave of a slave to allow another lower level slave control the bus as we have for our other Intel CPU boards. See for example here. This in all lightly hood would not be widely utilized with a chip like this however.

Finally as we shall see this board makes extensive use of one Atmel 1508 CPLD and two 22V10 GAL's. These greatly simplify the board circuits. However they need to be programmed. You will need as GAL programmer and a CPLD programmer. The source code for the CPLD and two GALs are discussed below as well a PC based IDE to write CPLD code should you wish to modify the boards software.

Introduction to the 80486
The Intel 80486 was an upgrade from its earlier very successful 80386 microprocessor. It was introduced in 1989. It was on the surface just a faster 80386 with the 80387 math coprocessor now onboard. The initial clock speed was 16 MHz, but over time this rose to 100M Hz. It reportedly contained over one million transistors.


	Intel 80486 CPU

From a performance point of view however, the architecture of the 80486 was a vast improvement over the 80386. The old 8086 style "bus-interface unit" (BIU) was considerably enhanced. Simple instructions (such as MOV reg, reg) executed in one clock cycle. There was no Motorola 68020 style cash on the 80386. The 80486 made up for this by having a large (8 KB) on-chip cache to store the most recently used instructions and data. All in all there was doubling of the chips performance over the 386 at the same clock rate. The 80486 was Intel's answer to AMD's 80386 that was beginning to eat into Intel's lead.

The dynamic bus sizing of the 80486 motherboards was increased from 32 and 16 bit data buses to also include the ability to squeeze the data path down to an 8 bit bus. Thus you only needed one BIOS/boot EPROM on a motherboard.

There were a large number of different 80486's produced over the years. Here are some of the major ones I have used with this board.

Intel 80486-DX
This CPU ran with core a frequency equal to bus frequency, introduced in May 1990. It was followed in June 1991 by the DX-50. Both chips at full speed ran hot. To run the DX-50 at 50MHz required a heat sink. To over-clock this chip, it required a heatsink-fan, with that it could run all day long at 60MHz. At the speed we run the CPU on our S100 board no heat sink is required.

Intel 80486-DX2
This chip was very popular with OEMs and system builders. The CPU internally ran at 2X the speed of the external bus. Unlike the DX-33 and DX-50, the DX2-50 didn't require a heat sink for use. Also unlike the DX series , the DX2 series didn't require OEMs to build quality advanced high speed clocked circuits throughout the motherboard. It was introduced in March 1992

Intel 80486-DX4
The 80486DX4 continued the trend started by the 80486DX2 toward faster clock speed processors on slower motherboards. The DX4 uses "clock tripling", where the processor runs at three (not 4), times the speed of the memory bus (motherboard). Intel's DX4 ran internally at two speeds: 75 MHz (for the 25 MHz bus) and 100 MHz (for the 33 MHz), with the 100 being by far the most popular. In order to keep power and heat to a manageable level the voltage of these chips was reduced to 3.3 volts. The Intel, AMD and Cyrix versions of the DX4 chip are quite similar. One difference was that the AMD and Cyrix support write-back cache while the Intel did not; however the Intel had its level 1 cache doubled to 16 KB. All three chips supported power management. The chip was first introduced in March 1994.

Intel 80486-SX
The Intel 80486SX is the same chip as the 80486DX with one exception: the lack of an integrated math coprocessor BTW, this is a different kind of difference between the SX and DX versions than is the case with the 386; the 386SX and 386DX both had no coprocessor and the 386SX had narrower data and address buses than the 386DX. The 486DX and 486SX have the same bus widths. Since it is the same chip except for the floating point processor, the 486SX had all the same advantages over the 386 that the 486DX had. The 486SX was available in slower clock speeds than the 486DX; the SX came in 16, 20, 25 and 33 MHz versions, while the DX came in 25, 33 and 50 MHz versions. The 486SX was a popular choice for laptops due to its lower cost and lower power consumption. The SX was introduced in April 1991.

AMD 5X86
Not introduced until November 1995, the AMD 5x86 was a standard 486 processor with an internally-set multiplier of 4, allowing it to run internally at 133 MHz on systems with clock-multiplied DX2 or DX4 486 processors. Like most of the later 486 parts, the 5x86 featured write-back L1 cache, and unlike all but a few, it had a generous 16 kilobytes rather than the more common 8KB. Since having a clock multiplier of four was not part of the original Socket 3 design, AMD made the 5x86 look for a two times setting from the motherboard and interpret that as four times instead. In other words, to use the 5x86 you want to set the motherboard to the 2x setting (JP17). This will actually cause the 5x86 to run at 4x. The combination of best-in-class clock speed and the write-back cache allowed the 5x86 to equal or slightly surpass an Intel Pentium 75 MHz processor in business application performance. Also, because it was based on a pure 486 design, it was compatible with older systems, something its slightly faster rival, the Cyrix 5x86, had trouble with.

As you can see from above it took AMD almost four years to come our with their 80486. It was lower priced and again faster, but it was too late to dominate the market.

As I described for our 80386 board, Cyrix came out with a "80486DLC" that was pin for pin compatible with the Intel 80386 chip. This chip could run 80486 opcodes and in fact had a small onboard cash, but it was nowhere close to the speed of a 168 pin 80486. It also did not have an onboard math co-processor.

Circuits of our 80486 CPU board
As for the 80386 CPU board we will build this board in stages.

	1	Build and debug a Master/Slave S-100 80486 CPU board such that it is completely self-contained and can run MS-DOS in the system on the S-100 bus. Using only an 8 bit S100 data bus
	2	Build and debug a Master/Slave S-100 80486 CPU board such that it is completely self-contained and can run MS-DOS in the system on the S-100 bus. Using both an 8 and 16 bit S100 data bus
	3	Build a ribbon cable connected S100 daughter RAM board utilizing very high capacity static RAM chips (16M chips).
	4	Build the same type of board utilizing very high capacity DRAM SIMMS (1GB SIMMS).

This is by far the most challenging S-100 board I have undertaken. I will detail things as we go along and welcome comments and suggestions along the way.
The board exists in two formats:-

The Baby 80486 board, this board can address up to 16MB of RAM on the S100 bus. It typically runs with a PHI clock of 8-9 MHz on the S100 bus. The board has an onboard 128K EEPROM containing the 80386 monitor and can run MSDOS as for our other 8 & 16 bit S100 boards including our S100 bus VGA Board.

The second board format which we will call the Full Size 80486 Board substitutes the onboard EEPROM circuit for the OTT connectors to allow it to address up to 4GB of RAM. Except for the onboard EEPROM it retains all the capabilities of the Baby 80486 board. The board has a dual CPU clock system. It runs at 8MHz on the S100 bus in 8 & 16 bit modes and 18MHz (or greater), when addressing RAM on the OTT bus in 8,16 or 32 bit modes.

Almost all the above capabilities are programmed into the onboard Atmel 1508 CPLD.   Most of the discussion below will be for the Full Size 80486 board. For the Baby 80486 board the appropriate code is simply not present. Let us step through the various functions/code this CPLD supplies.

1. Activate the board.
The current software assumes this 80486 board will act as an S100 bus slave. Later if needed, it can be modified/jumpered as being a bus master.
In hardware one of the TMA lines (Jumper P13) goes low to start the master/slave transfer process.
Just as for the 80386-II board, sequentially XFERI & XFERII are then activated (and the S100 bus clock signal PHI, then originates from this board).

Pinnode = [reg2..0];                       /* Need 3 D type Flip Flops */

reg0.d = TMAx;                             /* TMAx goes low-> high */
reg0.ckmux = !PHI;
reg0.ar = !MASTER_RESET;                   /* Return to high on reset */
!S100_HOLD = reg0;                         /* Lower S100 bus HOLD* line */

!XFERI = reg0 & pHLDA;                     /* Activate the S100 bus Control lines, when HLDA comes back */
                                           /* Note we inactivate U55 for RAM > 16M in protected mode */
reg1.d = reg0;
reg1.ck = pHLDA;                           /* S100 bus grants bus by raising pHLDA line */
reg1.ar = !reg0;

BOARD_ACTIVE = reg1;                       /* HIGH when transfer comes to 80486 Board */
!XFERII = reg1;                            /* LOW to activate S100 bus Status, Data & Address lines */

reg2.d = reg1;
reg2.ckmux = !PHI;
reg2.ar = !reg1;

!RESET_80386 = reg2;                       /* Activate the CPU, lower it's reset pin */

CPU_HOLD = 'b'0;                           /* CPU HOLD always low for Slave mode for now */

2. The Clock Generator/Divider Circuit
We will divide a 16 or 36 MHz (or higher), oscillator down to obtain the CPU and S100 bus clocks. CLK becomes PHI on S100 bus via U15. It is a different speed when Z80 is bus master clock, so remember PHI is not the same as CLK.

For the Baby 804896 board the clock system is quite simple:-

/*
* We need to divide the 36 MHz Oscillator down to obtain CPU and S100 bus clocks.
* Note CLK becomes PHI on bus via U15. It is a different speed when the Z80 is the bus master,
* Note the CPU will run at two clock speeds. Normally at 9MHz. But if the GAL U12 "SLOW_RAM"
* signal is LOW it will run at 2 MHz
*/

Pinnode = [CD3..0];
                                  /* MASTER_CLK = 36 MHz */
CD0.t = 'b'1;                     /* 18 MHz */
CD1.t = CD0;                      /* 9 MHz */
CD2.t = CD0 & CD1;                /* 4.5 MHz */
CD3.t = CD0 & CD1 & CD2;          /* 2.25 MHz */

[CD3..0].ckmux = MASTER_CLK;

DELAY_CLK = ((CD1 & SLOW_RAM)     /* DELAY_CLK speed for the 74LS164 Wait state generator */
          # (CD3 & !SLOW_RAM));   /* Extra long delays to access VGA/SLOW RAM */

CLK = CD1;

In the above we setup four toggle flip flops. We divide the input oscillator by two each time.  For S100 bus access we will have two clock speeds. A PHI of 9MHz or for older/slower RAM boards, 2.25 MHz.

Not all S100 systems may be able to work at 8-9 MHz, so even with the above you might want to start with a 20-32 MHz range of oscillators. Remember the 80486 has an internal RAM access cash buffer and for the DX series, a 2X or 3X internal speed-up of the clock signal (jumper JP17). This internal speed-up mode works fine with all RAM boards I used with this board.

The "DELAY_CLK" signal is used to generate wait states for the CPU. Because we need a wide range of wait states for new and old S100 RAM boards two clock speeds are used to generate the timing/jumper signals (see below).

For the Full Size 80486 board in Protected mode (using the OTT bus and greater than 16MB RAM) we run CLK at 16 MHz. The only fly in the ointment is when we switch clock speeds.   We have to be careful not to generate runt clock cycles. In the 74LXxx based 80386 board we used a 74LS74 chip (Clocked by CLK2) to do this. We do it here in software (see below). Note, the upper speed limit of these ATF 1508's is about 150MHz, so we could later add more flip flops and get more speed options.
Here is the clock switching CPLD code for the Full Size 80486 board.

/* Generate the dual frequency 80486 CLK signal and wait signal */

/* Pinnode = MASTER_CLK; */

Pinnode = [CD5..0];

/* MASTER_CLK = 32 - 40 MHz */

CD0.t = 'b'1;                                   /* 16 - 20 MHz */
CD1.t = CD0;                                    /* 8 - 10 MHz */
CD2.t = CD0 & CD1;                              /* 4 - 5 MHz */
CD3.t = CD0 & CD1 & CD2;                        /* 2 - 2.5 MHz */
CD4.t = CD0 & CD1 & CD2 & CD3;
CD5.t = CD0 & CD1 & CD2 & CD3 & CD4;

[CD5..0].ckmux = CLK1;

CLK   = ((LS100_SEL & CD0)
      # (!LS100_SEL & CD1));

DELAY_CLK = ((CD1 & SLOW_RAM)                    /* DELAY_CLK speed for the 74LS164 Wait state generator */
          # (CD3 & LS100_SEL)                    /* Extra long delays to access OTT RAM */
          # (CD3 & !SLOW_RAM));                  /* Extra long delays to access VGA/SLOW RAM */

Not all S100 systems may be able to work at 8MHz with the Full Size 80486 board, so even with the above you might want to start with a 10-16 MHz range of oscillators. Again remember the 80486 DX chips have an internal RAM access cash buffer and a 2X or 3X internal speed-up of the clock signal (jumper JP17). The internal speed-up mode works fine with all RAM boards I used with this board.

The "DELAY_CLK" signal is used to generate wait states for the CPU. Because we need a wide range of wait states for new and old S100 RAM boards two clock speeds are used to generate the timing/jumper signals (see below).

It is absolutely critical when the CPU switches from addressing the (fast) OTT RAM to the (slow) S100 bus that the CPU CLK speed immediately switches to the slow clock speed and that not even one high speed clock pulse is sent to the S100 bus. No "runt" pulsed can be tolerated. Overnight test testing with our 80386 "Y" command in PM mode is needed to be absolutely sure we have a rock solid setup. This command executes a small program in PM (moved from the ROM to a user defined RAM location e.g.. 2001234H). The program reads the I/O Byte port, and displays the ASCII code on the CRT. It goes back and forth between slow and fast speeds for RAM and I/O access repeatedly. This test must be 100% reliable to use the CPU in PM mode. It is the most restricting and brutal test for the hardware. Here is a picture of a logic probe display of the signals.

3. Activated the LS100_SEL* signal.
In the case of the Full Size 80486 board the CPU will be talking to two completely separate RAM circuits. For RAM below 16MB it will address RAM on the S100 bus. Any RAM above this address space will be assumed to be on the extended bus using the overhead connectors. All port I/O's and Interrupts will also be on the S100 bus. The relevant signal that defines which bus the CPU is talking to is the LS100_SEL signal. If it is low the S100 bus is being addressed. If it is high the "over the top (OTT) bus" is being addressed. The extra complication is that when addressing the OTT bus the CPU's clock (CLK) is doubled -- because that bus can handle a much faster speed.

Pinnode = S100_SEL;
Pinnode = SLAVE_ACTIVE;                           /* SLAVE_ACTIVE HIGH if 80486 has control of the bus */
                                                  /* HIGH if RAM > 16M else LOW */

LS100_SEL = S100_RAM & LMIO & BOARD_ACTIVE;        /* S100_RAM HIGH if > 16M else LOW */

The S100_RAM signal is delivered to the CPLD on pin 46 from pin 19 of the GAL U10 . The PALASM code for this GAL is very simple, we just watch the CPU high address lines for situations where A31 to A24 are not zero. However also we need to consider the situation upon CPU Reset/Initialization where these address lines are all high (see below).

/S100_RAM@ =    cA31 * cA30 * cA29 * cA28 * cA27 * cA26 * cA25 * cA24
             + /cA31 * /cA30 * /cA29 * /cA28 * /cA27 * /cA26 * /cA25 * /cA24

Note how we only raise LS100_SEL for RAM access (LMIO high), not for I/O or Interrupts.

Note in the case of the Baby 80486 board LS100_SEL does not exist since the board only addresses RAM on the S100 bus.

4. Activated the S100 Bus ROM.
As for the earlier 80286, 80386 CPU's the 80486 always starts at FFFFFFF0H upon reset. This is at the very top of the CPU's 4 GB memory address space. In contrast, the 8086 starts at 0FFFF0H (at the top of its 1 MB address space). It's usually convenient to write one BIOS/Monitor for both CPU's. We play a trick on the 80486 in that whenever its top 12 address lines are all high (only at the top 64K of the CPU's 4GB address space), these 12 address lines show up as all low on the S-100 bus. Thereby an 8086 BIOS/monitor ROM can be utilized.  The 80486 "thinks" its talking to a ROM in its top 64K when in fact its at 000F0000H - 000FFFFFH. On our 80286 and 80386 boards we did this with two line to one line converters, (74LS175's).

In working with this board (and the earlier 80386 board) , to my surprise I found that that this switching circuit was the Achilles heel of the board in terms of speed.   I have pulled the complete circuit into the high speed U10 GAL. (On our 80386 boards it was done in hardware). Here is the relevant PALASM code.

/mA23 = cA31 * cA30 * cA29 * cA28 * cA27 * cA26 * cA25 * cA24 * cA22 * cA21 * cA20
     + /cA23

/mA22 = cA31 * cA30 * cA29 * cA28 * cA27 * cA26 * cA25 * cA24 * cA23 * cA21 * cA20
     + /cA22

/mA21 = cA31 * cA30 * cA29 * cA28 * cA27 * cA26 * cA25 * cA24 * cA23 * cA22 * cA20
     + /cA21

/mA20 = cA31 * cA30 * cA29 * cA28 * cA27 * cA26 * cA25 * cA24 * cA23 * cA22 * cA21
     + /cA20

We simply force the S100 bus address lines A20-A23 low if the CPU is in the range FFFF0000H - FFFFFFFFH. This way the reset code at FFFFFFF0H is utilized in our 80386 (or 8086) monitor code at FFFF0H on the S100 bus.

Note the GAL zip files below contain the final .JED files if you just want to quickly burn the two GALs with all the code above to run these boards immediately.


5. Synthesize the Address lines A0 & A1 & sXTRQ* from the CPU BE3*... BE0*
This is fairly straightforward. We also need to generate the S100 bus signal sXTRQ for 16 bit access from the 80486 signals:-

mA1 = mBE0 & mBE1;                                /* From the Intel 80486 hardware Manual */

mA0   = (mBE0 & !mBE1 & !mBE2)
       #(mBE0 & !mBE1 & mBE2)
       #(mBE0 & mBE1 & mBE2);

LmsXTRQ = ((mBE1 & mBE3)                          /* HIGH for 8 bit Request, LOW for 16 bit request */
         # mA0);

BS8     = !LmsXTRQ & !SIXTN;                      /* See if RAM/IO Board can handle a 16 bit request. */

!BS16   = !LS100_SEL;                             /* Never 32 bit mode on S100 bus -- force to 16 (or 8) */

The use of the BS8 CPU input is where there is a major difference from the 80386. If this line is low the 80486 will send 32 or 16 bit data as two or four back to back 8 bit bytes. This capability did not exist on the 80386. It allows us to conveniently run 8 bit S100 boards with this 80486 CPU board.   The IEEE-696 specs. state that if a board is not capable of handling a 16 bit request (as indicated by the lowering of the S100 bus line sXTRQ), it will NOT return a lowered S100 bus line SIXTN.   That is why we use a low sXTRQ & low SINTN to raise BS8 indicating to the CPU that a 16 bit transfer is OK. It's very important to appreciate that this analysis is carried out "on the fly" for each CPU bus cycle. If an S100 bus board cannot return a low SIXTN quickly the 80486 will assume an 8 bit transfer is required. So far all our S100Computers seem to be fast enough to do this with a PHI of 8-9 MHz -- assuming a properly terminated S100 bus motherboard.

6. Synthesize the S100 Bus Control and Status signals
This is the very heart of the board. Just as for the 80386, we need to carefully reformulate the main 80486 control signals to their S100 bus counterparts. The signals are essentially the same as for the 80386 board:-

!IO_OUT = !LMIO & LDC & LWR & ADS;                                 /* I/O Write */

!IO_IN = !LMIO & LDC & !LWR & ADS;                                 /* I/O read */

!MEM_WR = LMIO & LDC & LWR & ADS & !LS100_SEL;                     /* RAM Write (data) for S100 bus only */

!MEM_RD = ((LMIO & !LDC & !LWR & ADS & !LS100_SEL)                 /* RAM code read for S100 bus only */
         # (LMIO & LDC & !LWR & ADS & !LS100_SEL));                /* RAM data read for S100 bus only */

!INTA = !LMIO & !LDC & !LWR & ADS;

!HALT = LMIO & !LDC & LWR & ADS;

!ssM1 = ((LMIO & !LDC & !LWR)                                      /* RAM code read for S100 bus only */
       # (!INTA));                                                 /* INTA */

ssWO = (!IO_OUT                                                    /* I/O Write */
     # !MEM_WR                                                    /* RAM Write */
     # !INTA);                                                    /* INTA (ALL) */

!dpWR = ((!IO_OUT & !Delay2 & !ppSync)                             /* Delayed I/O Write (ALL) */
      # (!MEM_WR & !Delay2 & !ppSync));                           /* Delayed RAM Write (S100 Bus only) */

ppDBIN = ((!MEM_RD & INTA & !ppSync)                               /* RAM read (S100 Bus only) */
       # (!IO_IN & INTA & !ppSync));                               /* I/O read (ALL) */

!EXT_RAM_WR = LMIO & LDC & LWR & ADS & LS100_SEL;                  /* RAM Write for overhead bus */

!EXT_RAM_RD = ((LMIO & !LDC & !LWR & ADS & LS100_SEL)              /* RAM Read for overhead bus */
            # (LMIO & LDC & !LWR & ADS & LS100_SEL));

All this is based on the data sheets Intel and AMD supplied that describes the levels of the critical M/IO, D/C and R/W control lines send out by the CPU.   See here for more details. Note these lines going into the CPLD are not latched as they were for the 80386.    For the S100 bus the problematic signal is the main pWR* signal. It stays low too long for the S100 bus (rising only when the address lines become invalid). The "Delay_2" signal is provide by the jumper P14 to correct this.
Here is a picture of the CPU and shortened S100 bus pWR* signals:-

Note how the S100 bus pWR* signal only goes low after pSYNC returns low and rises when Delay2 rises. The 80486 holds its RAM/ IO write signal low for too long on the S100 bus. It raises it just as the address lines are no longer valid. Many S100 boards need pWR* to rise earlier in the cycle. As a side note, all our S100Computers.com boards will accept pWR* going low initially (when pSYNC going high), however some older bus 1980's era boards do not. You can play around with this code if you like:-

!dpWR = ((!IO_OUT & !Delay2)                             /* Delayed I/O Write (ALL) */
      # (!MEM_WR & !Delay2));                           /* Delayed RAM Write (S100 Bus only) */

Besides the above early termination of the pWR* signal, we need to stretch out the CPU RAM and I/O access times with "wait states". This is dependent on the RAM and I/O boards in your system. Somewhere between 3 and 4 MASTER_CLK cycles seems best in most cases. However their values must always be greater than the DELAY_2 jumper setting described above.   Remember also, the DELAY_CLK signal going to U31 the wait state generator is the full speed Phi clock, so each jumper is one S100 bus clock cycle. Here is a picture of the jumpers for the Baby 80486 board using a 36 MHz Oscillator (Bus Phi = 9 MHz):-


	Baby 80486 Wait State Jumpers

Here is a picture of the jumpers for the Full Size 80486 board using a 16 MHz Oscillator (Bus Phi = 8.0):-

With these arrangements the 8 bit VGA video board does not need any wait states for its SW1 and SW2 switches to run MSDOS. This arrangement also works fine with the later IEEE-696 RAM boards such as the CompuPro RAM 21 board. Very old S100 bus RAM boards will require a slower speed and probably some wait state tweaking. However these CPU boards are really meant to work with our high capacity fast multi megabyte RAM boards. You can generally trim down the above wait state numbers, particularly if you don't need the 8 bit VGA board access, but this jumper arrangement is a good place to start.

In the first version of the 80386 board I sent LMIO, LDC and LWR over the top of the board (via the OTT bus) to the 32 bit RAM boards. These boards would decode the signals to generate the corresponding RAM read and write signals on the RAM board itself.   As for the 80386-II board I found it is more reliable to do the decoding on this board in the CPLD and just send the RAM read or write signals directly.    The two signals EXT_RAM_RD and EXT_RAM_WR are these signals. There are jumpers (K103 & K106) to utilize the "old" signals if you wish to utilize the earlier RAM boards. All newer OTT RAM boards however will utilize these two signals only. The Baby 80486 board does not need/have the EXT_RAM_RD and EXT_RAM_WR signals.

Please note this board will NOT work the V5.0 or V5.1 16MB Static RAM boards. This is because of an error on those boards where the S100 bus signal SIXTN* was not brought out to the bus via an OC gate. A patch was provided for those boards, but if possible use the newer V6.0a Static RAM board.   All the older S100Computer 4MB RAM & 16MB RAM boards work fine.

Note for the Full Size 80486 board, the OTT RAM boards do require 1 wait state on the RAM board itself for reliable operation. (Jumper P1003, 1-2, on the V2 board) as none of the above S100 bus wait state circuit is active during OTT bus access.

As I said the above, this code module is the very heart of both boards. Quite a bit of work went into analyzing these signal and optimizing them for various S100 bus boards. All our S100Computers.com boards appear to work reliably at 8MHz with the above code. That said, the power of the CPLD is that these S100 bus signals are completely configurable. You can use P14, Delay_2 (and K4, Delay_1, currently unused), to modulate any S100 bus signal.


7. Generate CPU Ready* signal.
If the 80486 READY input signal is HIGH then the CPU will add wait states until it is LOW again. The clock going to the wait state generator circuit (U31) is DELAY_CLK, so each jumper setting is 1/2 of a CLK cycle -- an actual S100 bus cycle wait state. That said, even at 8MHz the S100 bus the board requires 2 - 3 wait states for RAM and I/O access.   See above for a suggested setting to start with.

Again remember, in protected mode when access the OTT RAM boards is taking place the above wait states are not inserted. Those boards have their own wait state generator which returns the "DB_WAIT" signal to the CPLD (pin 15) to request a wait state. With a 16 MHz CLK signal only a single CLK wait state is required with our current OTT RAM boards.

/* Generate CPU Ready* signal. If READY is HIGH then the CPU will add wait states until it returns LOW again */

Pinnode = RAM_CYCLE_WAIT;
Pinnode = IO_CYCLE_WAIT;
Pinnode = INTA_CYCLE_WAIT;

!RAM_CYCLE_WAIT = ((!RAM_WAIT & LMIO & !LWR & ADS & !LS100_SEL)            /* RAM Read Data or Code */
                 # (!RAM_WAIT & LMIO & LDC & LWR & ADS & !LS100_SEL));     /* RAM Write Data */

!IO_CYCLE_WAIT = ((!IO_WAIT & !LMIO & LDC & LWR & ADS)                     /* I/O Write Data */
                # (!IO_WAIT & !LMIO & LDC & !LWR & ADS));                  /* I/O Read Data */

!INTA_CYCLE_WAIT = !INTA_WAIT & !LMIO & !LDC & !LWR & ADS;                 /* INTA cycle */

READY = ((!S100_WAIT & BOARD_ACTIVE)
       # (!RAM_CYCLE_WAIT & BOARD_ACTIVE)
       # (!IO_CYCLE_WAIT & BOARD_ACTIVE)
       # (!INTA_CYCLE_WAIT & BOARD_ACTIVE)
       # (!DB_WAIT & LS100_SEL & BOARD_ACTIVE));

S100_WAIT is generated by other bus S100 boards. The two S100 bus wait request signals XRDY* and RDY* are captured by U5.
There is also another input to U5 which is very useful for single stepping the board once control has been transferred to it on startup (via Jumper K101). This is described below.

8. Generate buffer control signals for 8/16 bit CPU transfers to S100 bus data lines using the IEEE-696 protocol
One nice thing about using a CPLD is there is now ample room to lay down detailed equations so we can convert the 8 or 16 bit data signals to/from the 80486 and redirect them to the appropriate 8 or 16 bit S100 bus data lines. If you are not familiar with the unique way the S100 bus handles 8 and 16 bit data please see here first.

Let us consider the full Size 80486 board first. As for our 80386 board, a fundamental split in how the CPU functions is determined by whether the CPU is operating in "Protected" or "Real" mode. If the former, AND the CPU wishes to address RAM above the 16MB range of the S100 bus the address, data, and control signals do not travel on the S100 bus (they would have no function anyway) but to RAM board(s) connected via the top "over the top" (OTT) ribbon cable connector bus. Our GAL (U12) identifies this situation by continuously looking at the CPU's high order address lines and control lines. Any time the 80486 addresses RAM above 16MB it lowers the S100_SEL* line. This important signal originate from pin 19 of U10. If S100_SEL* is high the CPU directs ALL its signals to the OTT bus. If S100_SEL* is low it directs all its signals to the S100 bus. So in many of the CPLD equations you will see terms line "& S100_SEL" or "& !S100_SEL".

A second signal SLOW_RAM* is also produced by GAL (U12) pin 20. This signal is low if the CPU is addressing RAM on the S100 bus that requires a longer access time. Currently it is setup for RAM in the range of A0000H-BFFFFH. This is the range of RAM supplied by our S100 VGA board. This board (which accepts only 8 bit access) and is incapable of running correctly at 8Mhz. Any access to the RAM on that board will be at 2MHz. The good news is that at 2MHz no wait states are requires on the VGA board.

How data moves from the CPU to the S100 bus and the boards OTT 32 bit bus is directed via the 4 bus 74LS245 data bus drivers U7 ,U8, U13 and U8. For S100 bus access the data will always be restricted to 8 or 16 bit data paths. 32 bit data will not be allowed.   This is accomplished by pulling the 80486 CPU pins C17 and D16 low whenever we access the S100 bus (RAM or I/O's).   All we have to do is activate one or more the above four CPU data bus drivers. Which one is determined by the RAM or I/O ports address. For RAM addresses X+0 we use data lines 0-7 with BE0*, for X+1 we use data lines 8-15 with BE1*, for X+2 we use data lines 16-23 with BE2*, and for X+3 we use data lines 24-31 with BE3*. The complication we have is the upper bytes of the CPU's data have to be redirected downwards to the S100 bus 8 or 16 bit data bus and sent out on the S100 bus buffers U103, U104, U105 then U112, U111, U113 (and for 8 bit data U117 and U116). This required some very tricky CPLD code and a thorough understanding of how the 80486 handles its data lines. Fortunately Intel described the process well in its 80486 technical manual.

For RAM above 16MB on the OTT bus things are much simpler. Its a full 32 bits wide bus so all we have to do is be sure the S100 bus data circuit is not involved. This is accomplished with S100_SEL* feeding the four 74LS32 gates to the OE* pins of the above 74LS245 drivers U7 ,U8 ,U13 and U8 and inactivating them. The OTT RAM board will handle the rest (it decodes BE0-3* on the RAM board).   Here is the relevant code to enable the relevant bus buffers:

/* Generate buffer control signals for 8/16 bit CPU transfers to S100 bus data lines using IEEE-696 protocol */
/* See Intel 80486 hardware manual to understand */

/* >>>>>>>> First take care of 8 bit data paths. (Note these are all OFF for 16 bit data) <<<<<<<<<<<<<< */

                                                                                       /* Ax+0, no crossover buffers open.*/

!BEN8H = ((!LS100_SEL & !mBE3 & !mBE2 & !mBE1 & mBE0 & !BS16 & !BS8 & BOARD_ACTIVE)    /* Ax+1, 8 bits */
        # (!LS100_SEL & mBE3 & !mBE2 & !mBE1 & mBE0 & !BS16 & !BS8 & BOARD_ACTIVE)
        # (!LS100_SEL & mBE3 & mBE2 & !mBE1 & mBE0 & !BS16 & !BS8 & BOARD_ACTIVE));

!BEN8UL = ((!LS100_SEL & !mBE3 & !mBE2 & mBE1 & mBE0 & !BS16 & !BS8 & BOARD_ACTIVE)    /* Ax+2, 8 bits */
         # (!LS100_SEL & mBE3 & !mBE2 & mBE1 & mBE0 & !BS16 & !BS8 & BOARD_ACTIVE));

!BEN8UH = ((!LS100_SEL & !mBE3 & mBE2 & mBE1 & mBE0 & !BS16 & !BS8 & BOARD_ACTIVE));   /* Ax+3, 8 bits */

!S100_8_IN_OE = ((!LS100_SEL & !LWR & !BS16 & !BS8 & BOARD_ACTIVE)                     /* 8 bits in to CPU */
               # (!LS100_SEL & !INTA & BOARD_ACTIVE));                                 /* Enable INTA acknowledge */

!S100_8_OUT_OE = ((!LS100_SEL & LWR & !BS16 & !BS8 & BOARD_ACTIVE));                    /* OE* 8 bits out from CPU */

/* >>>>>>>>>>> Now take care of 16 bit data paths. (Note these are all OFF for 8 bit data) <<<<<<<<<<<<< */

!BEN16LH = ((!LS100_SEL & !mBE3 & !mBE2 & !mBE1 & !mBE0 & !BS16 & BS8 & BOARD_ACTIVE)   /* Ax+0, 16 bits */
         # (!LS100_SEL & mBE3 & !mBE2 & !mBE1 & !mBE0 & !BS16 & BS8 & BOARD_ACTIVE)
         # (!LS100_SEL & mBE3 & mBE2 & !mBE1 & !mBE0 & !BS16 & BS8 & BOARD_ACTIVE)
         # (!LS100_SEL & mBE3 & mBE2 & mBE1 & !mBE0 & !BS16 & BS8 & BOARD_ACTIVE)
         # (!LS100_SEL & !mBE3 & !mBE2 & !mBE1 & mBE0 & !BS16 & BS8 & BOARD_ACTIVE)      /* Ax+1, 16 bits */
         # (!LS100_SEL & mBE3 & !mBE2 & !mBE1 & mBE0 & !BS16 & BS8 & BOARD_ACTIVE)
         # (!LS100_SEL & mBE3 & mBE2 & !mBE1 & mBE0 & !BS16 & BS8 & BOARD_ACTIVE));

!BEN16UH = ((!LS100_SEL & !mBE3 & !mBE2 & mBE1 & mBE0 & !BS16 & BS8 & BOARD_ACTIVE)      /* Ax+2, 8 bits */
         # (!LS100_SEL & mBE3 & !mBE2 & mBE1 & mBE0 & !BS16 & BS8 & BOARD_ACTIVE)
         # (!LS100_SEL & !mBE3 & mBE2 & mBE1 & mBE0 & !BS16 & BS8 & BOARD_ACTIVE));

The Baby 80486 has a slightly different configuration. For this board there is no LS100_SEL since we are only addressing S100 bus RAM. However the board does have an 8 bit onboard 128X8K 27C101 EPROM (or better GLS29EE010 EEPROM equivalent). This onboard ROM is activated via SW3 (bottom LHS of board).
If that switch is closed the input to pin33 of the CPLD will be low. This activates a flag whenever the CPU is in the range 0F0000-0FFFFFH.

!ONBOARD_ROM = !ENABLE_ROM & !ROM_SEL; /* To activate onboard ROM */

Note the SW3 switch is labeled "Diagnostic_SW1" on the board silkscreen.

ROM_SEL* is from the GAL U12, pin 19. When this happens data in from the S100 bus should be stopped. The code below does this.

                                                                         /* Ax+0, no crossover buffers open. */

!BEN8H = ((!mBE3 & !mBE2 & !mBE1 & mBE0 & !BS8 & BOARD_ACTIVE)           /* Ax+1, 8 bits */
        # ( mBE3 & !mBE2 & !mBE1 & mBE0 & !BS8 & BOARD_ACTIVE)
        # ( mBE3 & mBE2 & !mBE1 & mBE0 & !BS8 & BOARD_ACTIVE));

!BEN8UL = ((!mBE3 & !mBE2 & mBE1 & mBE0 & !BS8 & BOARD_ACTIVE)           /* Ax+2, 8 bits */
         # ( mBE3 & !mBE2 & mBE1 & mBE0 & !BS8 & BOARD_ACTIVE));

!BEN8UH = ((!mBE3 & mBE2 & mBE1 & mBE0 & !BS8 & BOARD_ACTIVE));         /* Ax+3, 8 bits */

!S100_8_IN_OE = ((!LWR & !BS8 & ONBOARD_ROM & BOARD_ACTIVE)
              # (!INTA & BOARD_ACTIVE));                                /* Enable INTA acknowledge */

!S100_8_OUT_OE = LWR & !BS8 & BOARD_ACTIVE;                             /* OE* 8 bits out from CPU */

!S100_ROM_IN_OE = !MEM_RD & !ONBOARD_ROM & BOARD_ACTIVE;

/* >>>> Next take care of 16 bit data paths. (Note these are all OFF for 8 bit data) <<<<*/

!BEN16LH = ((!mBE3 & !mBE2 & !mBE1 & !mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM)          /* Ax+0, 16 bits */
          # ( mBE3 & !mBE2 & !mBE1 & !mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM)
          # ( mBE3 & mBE2 & !mBE1 & !mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM)
          # ( mBE3 & mBE2 & mBE1 & !mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM)
          # (!mBE3 & !mBE2 & !mBE1 & mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM)           /* Ax+1, 16 bits */
          # ( mBE3 & !mBE2 & !mBE1 & mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM)
          # ( mBE3 & mBE2 & !mBE1 & mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM));

!BEN16UH = ((!mBE3 & !mBE2 & mBE1 & mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM)            /* Ax+2, 8 bits */
          # ( mBE3 & !mBE2 & mBE1 & mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM)
          # (!mBE3 & mBE2 & mBE1 & mBE0 & BS8 & BOARD_ACTIVE & ONBOARD_ROM));

While the onboard EPROM/EEPROM is great for debugging the Baby 80486 board, as soon as you have it working you should switch to the normal situation where we use the 16 bit wide ROM's on the MSDOS Board. This is because the above ROM based CPLD code works only in 8 bit mode. To take advantage of this CPU you need to be running the hardware in 16 bit mode (SW3 Open).

Unfortunately all the above code is quite complicated and requires a very careful study of how the 80486 presents data on its four 8 bit data busses for 8, 16 and 32 bit modes. Fortunately Intel explains it well in their 80486 technical manual. Here is how the various data buffers are arranged.

There are some 16 control signals that must be modulated for the above pathways to work correctly for all data paths.

9. Generate the S100 Bus pSYNC and pSTVAL signals
Finally we need a few housekeeping signals. We will generate the S100 bus signal pSTVAL (Low) = ADS* (CPU Low), Synchronized against it with the falling ADS* signal. We will generate the S100 bus signal pSync (High) = !ADS (CPU Low), (pSYNC is inverse of pSTVAL on this board).

ppSTVAL.ckmux = CLK;
ppSTVAL.d     = ADS;                    /* ADS Active LOW so in STVAL */
ppSync        = !ppSTVAL;                /* pSYNC is active high */
CPU_HOLD      = 'b'0;                    /* For now ignore */

All the above CPLD code can be quickly and easily generated utilizing the Atmel "WinCUPL" Windows IDE interface. You can read more about this interface here.

Note the CPLD zip files below contain the final .JED files if you just want to quickly burn the CPLD with all the code above to run these boards immediately.

9 Activating the Bus Slave CPU Board.
We still retained one 22V10 GAL (U101) to handle the master/slave switching circuit as we did for the 80386-II board.
Here is the PALASM code:-

;---------------------------------- PIN Declarations ---------------
PIN 1 PULSE_IN           ;CLK pin, input from pin 23 (PULSE_OUT)
PIN 2 A0                 ;Note these are actual S100 bus address lines (outside the 80386)
PIN 3 A1
PIN 4 A2
PIN 5 A3
PIN 6 A4
PIN 7 A5
PIN 8 A6
PIN 9 A7
PIN 10 A8
PIN 11 A9
Pin 12 GND

Pin 13 A10
Pin 14 A11
Pin 15 A12
Pin 16 A13
Pin 17 A14
Pin 18 A15
Pin 19 pDBIN              ;S100 bus port write
Pin 20 sINP               ;S100 bus status Port IN line
Pin 21 /RESET             ;Active LOW reset pulse from S100 bus
Pin 22 TMAXPU             ;Toggle bit to TMA 1-4 (inversed)
Pin 23 PULSE_OUT          ;Pulse to clock pin 1 input

;----------------------------------- Boolean Equation Segment ------

EQUATIONS

/PULSE_OUT =   A0 * /A1 * A2 * A3 * /A4 * A5 * A6 * A7              ;Port EDH = 1110 1101
            * /A8 * /A9 * /A10 * /A11 * /A12 * /A13 * /A14 * /A15
            * sINP * pDBIN
            + RESET * TMAXPU                                        ;Clock LOW if HIGH with reset

TMAXPU    := /TMAXPU * /RESET                                       ;Toggle
           + RESET

Here is the relevant circuit:-

10 Programming the Onboard EEPROM on the Baby 80486 Board.
The Baby 80486 board has a socket that will take a few different types of EPROMS. If you anticipate doing a lot of programming of the 80386/80486 monitor you are best off using a EEPROM such as the 128K X8 Greenliant GLS29EE010 (Mouser Part #: 804-GLS29EE010-70PHE). You can also use the older UV EPROMS. One note of caution. You have to be careful where you place the code in these large EPROMS. Since the current monitor only occupies 64K and starts at 0F0000H, we need to place the code in the "top half" of the 128K ROM. If you are using the Wellon VP290 burner this is what the code should look like.

Note how the last 16 bytes in the ROM is the start of the 80486 reset code in the monitor. See here to view the actual monitor code.

Differences Between the Baby and Full Size 80486 boards
The main difference between these two boards is the Full Size board is a 4 layer board. This was necessary to accommodate the numerous traces that must go to the top OTT bus for up to 4 GB of RAM.   This has allowed some of the critical signal lines to be much wider than on the baby board. With this arrangement the CPU can be centrally placed on the board allowing short traces to the 32 data and address lines of the OTT bus connectors. The is however no onboard ROM on the full size board. It is really meant to work hand in hand with our MSDOS Support Board.   The board is built so that it will work seamlessly with a 4GB DRAM board (currently being developed).

HARDWARE & LAYOUT
The Address Lines
The address lines of the 80486 (all 32 of them) are fairly standard. While better than the 80386, they still have limited drive capacity and except for small dedicated systems need drivers. Since we will be driving potentially up to 20 other cards in the S100 bus and one or more daughter RAM boards, we will clearly need 74LS244's.   Because the 80486 can address bytes (8 bits), words (16 bits), or double words (32 bits) there is no address line A0 and A1. Instead there are 4 "Bank Enable", lines BE0*-BE3* that select byte word or double word memory access. I'm assuming that you understand this concept if you are reading about a CPU of this complexity. If not there are countless descriptions/illustrations on the web. While on this topic, if you will be interested a further understanding of this CPU you should get one of Barry Brey's "The Intel Microprocessors" books. There are many editions, the later the better. I have the 7th edition.

RAM Boards.
In order to really utilized the full power of the Full Size 80486 board you need an OTT memory board. This is a work in progress. Currently we now have a 32/64 MG Static RAM OTT board. Later I hope to build a very high capacity DRAM board. To run this board with MSDOS and our MSDOS-Support Board its essential that U6 on that board be a 74F244, otherwise you may get false interrupts.

Remember for RAM above 16MB the OTT bus (daughter RAM board) runs at the full 18 MHz (and in 2X internal CLK mode). The 80386 monitor has a simple test routine (the "Y" PM mode command), that continuously reads the SMB IOBYTE port and outputs the corresponding ASCII character on the console (the Propeller driven Console IO board). This is the acid test for this hardware because the 80486 is continuously switching between S100 bus 8/16 bit access and the overhead 32 bit wide RAM access in cash enabled 2X clock mode. The former at 8MHz and the latter at 18MHz, the routine should be specified to be a RAM location above the S100 buses' 16M range (e.g. 2000000H).

There are a number of other tests within the current version of the 80386 monitor (V1.46). In particular the "J" command tests RAM (for RAM above the 16MB range) extensively to make sure values do not change over time or with writes to other locations. Keep in mind however that this test for 32MG of RAM takes a few hours to run. It is best to run it overnight.


Board Configuration. Master/Slave Bus Control
Another CPU is the Bus Master Calling our 80386 Slave Controller
This is the normal case for this 80486 board. Typically one boots up the S100 system with a Z80 CPU board. That board is designated the bus master.
For the case where another board is controlling the bus after reset, and our 80486 (as a slave) requests temporary control in a process as follows.

We activate our "slave board" by lowering any one of the four S-100 DMA lines (DMA0*, DMA1*, DMA2* or DMA3*). The board actually has an S100 I/O port (EDH), (using the U101, a 22V10 GAL), that also allows you to do this directly simply by inputting from this port.   In any event the input to pin 9 of U109 goes low.   This is fed to the CPLD, pin 73 which (via the CPLD pin 77) lowers the S-100 HOLD* bus line (pin 74). This signals to the bus master (usually a Z80) that our 80486 board wants control of the bus.   One clock cycle later the XFERI* line is lowered, activating the boards control lines to U32. As described above meanwhile, the bus master is inactivating its adderss+data+status lines. One clock cycle later, the 80386 boards own adderss+data+status lines are activated via XFRRII*. One clock cycle later the 80486 CPU is released allowing the CPU to control the bus.

Note that while we call the second CPU above the slave or temporary controller, there is nothing temporary or short time about it. Once transfer is given to the slave controller (the 80486 in our case) it has control of the bus as long as it wants. All day if necessary!

Transfer is given back to the bus master by inputting again from the same port reversing exactly the sequence of events described above.

While probably not needed, in theory the S-100 bus could have up to 15 possible slave controllers, indeed more, if onboard port activations are used. Thinking ahead with long term multi-board layout plans I have decided that I will always assign DMA0* to the 8088, 8086, 80286 80386 & 80486 family of CPU boards (using one in the bus at a time).   Likewise I have assigned the DMA1* line for the 68000, 68010 and any future Motorola CPU's. This leaves the DMA2* and DMA3*. This in the future, in combinations, would allow up to four other slave controllers on the bus.   I will be doing a DMA controller board in the future that will utilize these lines. Note however that because our boards also have an "activation" ports on board there is no limit to number of slave controllers in the bus.   For example while our 6502 CPU slave board could be activated by lowering DMA2*, it can also be activated via its own I/O port.

I should point out the IEEE-696 specification actually goes further than this. It allows the 1+15 Controllers to on the fly, prioritize which one has the bus at any one time by giving each board a priority number (4 bits, via a switch). See page 258 of the Sol Libes and Mark Garetz book Interfacing to the S100 Bus for example.    The problem with this approach is the software overhead becomes very complex. Minimally you would have to have a general circuit to read the status of the DMA lines as well as a number of processor specific routines to handle randomly striking interrupts etc.

With the approach I have here things are somewhat less complicated because the port calling program always knows the status of the CPU/DMA controller it is working with.

This board as the Bus Master Calling and other S100 Bus Slave Controllers
In this configuration the 80486 will signon upon reset and immediately control the S100 bus (instead of, for example, the Z80 board). This will normally not be a common situation since it requires a fairly sophisticated system of support boards and software. The reader should read carefully my description of these types of systems first described for our 80286 CPU board. The only difference here is we do all the switching hardware in the CPLD code. The relevant switching code is shown here:

/*
* Activate the board. >> NOTE THIS MODIFICATION OF THE CPLD CODE ASSUMES THE BOARD WILL RUN AS A BUS MASTER <<
* For a Slave (the usual mode), see the Bus Slave Version
*/

Pinnode = [reg2..0];               /* Need 2 D type Flip Flops */
Pinnode = BOARD_ACTIVE;            /* BOARD_ACTIVE HIGH if 80386 has control of the bus, see below */
Pinnode = ONBOARD_ROM;             /* Low if we use the onboard ROM */

BOARD_ACTIVE = MASTER_RESET;       /* In S100 bus master mode, board is active after reset returns HIGH*/
!RESET_80486 = BOARD_ACTIVE;       /* Let the CPU run */

reg0.d = !S100_HOLD & TMAx;        /* S100_HOLD will be LOW, unless a slave requests the bus then its HIGH. */
reg0.ckmux = !PHI;
reg0.ar = !MASTER_RESET;
CPU_HOLD = reg0;                   /* To CPU, HOLD will be LOW, unless a request is sent to the CPU from a slave */
pHLDA = reg0;                      /* Raise pHLDA to let slave know it has bus */

reg1.d = CPU_HLDA;                 /* CPU_HLDA back from CPU returns HIGH it's ready to grant the bus */
reg1.ckmux = PHI;
reg1.ar = !MASTER_RESET;
XFERII = reg1;                     /* LOW = active */

reg2.d = reg1;                     /* CPU_HLDA back from CPU returns HIGH it's ready to grant the bus */
reg2.ckmux = PHI;
reg2.ar = !MASTER_RESET;
XFERI = reg2;                      /* LOW = active */

ADD_DATA_STAT_DIS = !XFERII;       /* LOW disables S100 bus control of Address, Status & Data lines */
CDSB = !XFERI;                     /* LOW disables S100 bus control lines */

You will also need to change the jumpers P104 3-4, K104 1-2, JP101 and JP103. The resistor arrays RR1 and RR3 also need to be inserted.

CPU Chip Removal
Care is needed in removing the 80486 CPU from a PC motherboard or this board. Both the Intel and AMD chips are ceramic and are the (gold plated) pins are quite strong. I have found the easiest way to remove these chips is to insert a screwdriver all around the edge of the chip between the CPU and socket, each time twisting the screwdriver as you go around. See here:-

Do not try and release one side completely and then the other. If you do this you will bend the pins. Three or four cycles is necessary (particularly with a new socket). To insert the chip in its socket its absolutely essential to check that all the pins are lined up correctly. Look from the edge of the chip in all directions. Once a pin is bent its very difficult to realigned it. When you think all pins are in their sockets only then firmly press the chip into place.

Step By Step Building the 80486 CPU Boards.
The build instructions are fairly simple for this board but because it is a complex board building it should not be rushed. One important note of caution for even the most experienced S100 board builders. The traces on this board are very dense. In many cases two traces run between two IC pins. Also some critical lines such as the CPU Clock, pDBIN, pWR* etc. are extra wide for better signal quality. Try to add as little solder as possible -- just enough to make the contact to avoid cross bridges. For the CPU socket I actually have it raised a little from the board to insure the pins on the front side don't touch any traces. Solder one pin with something between the socket and board. Then the diagonally opposite pin. Then the rest of the pins. That way there is an "air space" beneath the socket and board with less danger of solder "smudging" across to a nearby trace. Great care should be also taken in this respect with the top two OTT ribbon cable connectors on the Full Size board. The address lines from the 80486 go directly to these pins. A short/cross bridge will inactivate the CPU and is difficult to debug. If in doubt check the pins before adding any components.

As always, first examine the bare board carefully for scratches or damaged traces, use a magnifying glass if need be. A broken trace is almost impossible to detect by eye on a completed board. (BTW, the copper on this board is thicker than for our previous boards -- again for better signals).

I find it useful to carefully slide a file at 45 degrees along the edges (front & back, sides) of the S100 connectors for easier insertion into the bus. Carefully, just one or two strokes.

Assembly of the Baby 80486 Board.
We will now build the board up in functional steps. Avoid the temptation of adding everything at once and popping it into your S-100 box. Step by step is faster in the end -- trust me. We will set the board up configured as an S-100 bus slave. Inputting port 0EDH (in my system, a Z80 monitor "W" or "O" command), will switch in this 80486 CPU board and switch out the Z80.

Solder in all the required IC sockets, resistors, resistor arrays, capacitors, jumpers, and the 5V Pololu voltage regulator and if required the 3.3V regulator. Do not add the LED's yet. Be sure you put the resistor arrays in with the correct orientation of pin 1. Check their values before soldering (they are difficult to remove). Remember if you already have 1K pull-up resistors for the S-100 bus vector interrupt lines and DMA lines in your system (for example on your Z80 CPU board), you really don't need the resistors on this board (RR1 & RR3). You can insert single row sockets such as Jameco #78624 in case you want to add pull-up resistors in another system. Be sure and insert the CPU and CPLD socket correctly with the notch at the bottom left-hand corner. Add the 2MHz Oscillator to P10.

The Pololu 5 Volt (and if required), 3.3 Volt regulators must not touch the traces under them. Use the straight 5 pin connectors supplied with them. The CPU seems to work fine with the 2.5 Amp regulators, the 5 Amp ones are not required.

For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets. However they are more expensive and you have to be particularly careful not to bend the IC pins. The two clock oscillators can have their own special sockets (e.g. Jameco #133006) but actually I find the "Machine Tooled" IC sockets make a better connection. I in fact solder the 2MHz oscillator directly to the board since it will never be changed.

Next insert all 5 LED's. Before soldering them in place ground the appropriate pin on the U15 socket to make sure it lights up.   I use a blue LED for 80486 active.

Check the voltage to sockets on the board is above 5V by placing the board in your S-100 system using an extender board. With no load you will typically get 5.00V (+/- 0.25V). BTW, your system should boot and run correctly with its Z80 master CPU board. If not, you have a serious solder bridge somewhere on the board. Before you do anything else with a magnifying glass go over every socket on the board and examine for a proper solder joint. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins. Double check.   Extra time here will save you hours later, (Been there, done that! ). Here is a picture of the board at this stage.

We will next add jumpers and IC's to the board. While on jumpers, please note every time when we talk about jumpers, position 1 is the square pad of the jumper. In order to minimize board trace lengths, its actual position/orientation on the board will differ from jumper to jumper. Sometimes they are top to bottom or left to right, other times the exact opposite. An incorrect jumper can be a real pain in debugging a non-working board. Check with the board schematic each time, to be sure . Make sure you correctly identify pin 2 in each case.

Burn the two GAL's using the JED code at the bottom of this page. You can use a Wellon VP290 or similar "Prom Burner".
486_GAL0.JED is for the U101 GAL, 486_GAL1.JED is for the U12 GAL. Both are Lattice 22V10's. See here for more information on GALs.

Add the main clock oscillator P5, 36MHz.
Next program the 1508 CPLD (U110). We do this now because we don't want pin I/O conflicts on the bus later. See here for more information on CPLD programming. The .JED file is provided at the bottom of this page.

Add both GALs to the board. Add U102 and jumper P13 1-2.
Use the Z80 monitor "O" command (input port EDH) and check that the jumper on P13 toggles High->Low--> High...
Add U14, U15, U109 and jumper K108 1-2, K104 1-2 and P104 1-2. Add jumper P102.

Repeat the "O" command test. The (blue) D1 LED should light up - possibly others.
If this does not happen, within the CPLD code, below "\* Activate the board....", use the Diagnostic LED to determine where the problem is.

Here is a picture of the board at this stage.

Check and be sure pin1 of U2, U3 & U4 goes from High to Low with the "O" command.
Add U2, U3 & U4, repeat the above test.
Add U5.
Repeat the "O" command test. The (blue) D1 LED should light up.

Add U6, U7, U8 & U13. On power on check that in all cases +/- "O" command pins 1 & 19 of each remain low.
Repeat the "O" command test. The (blue) D1 LED should light up.

Add U103, U104, U105, U16, U111, U113 & U114. On power on check that in all cases +/- "O" command pins 1 & 19 of each remain high.
Repeat the "O" command test. The (blue) D1 LED should light up. (LEDs D2 and D3 also will light up).

Add U32, U33, U117 & U116.
Repeat the "O" command test. The (blue) D1 LED should light up.
In this case Pins 1 & 19 of U32 and U33 should go low.

Add U31, U40 & U11. Add Jumper JP8, K101 2-3, K1 2-3, JP9 (MWRT), JP17 & K2 2-3 (off).
Jumper the wait state jumpers as shown here:-

Make sure all 4 switches on SW1 are off. Here is a picture of the board with everything added except the CPU

Next we will add the CPU. If you have a choice I suggest you first try the board with a cheap/common 80486/DX. Ideally one from a working PC motherboard. If you use a rare/expensive AMD chip or the (even rarer), 80486 DX4. Be absolutely sure the K3 jumper is set for 3.3Volts on its center pin. Measure this to confirm before adding the chip. See the write-up above for adding/removing these chips.

Carefully insert the 80386 CPU in it's socket. Remember pin 1 is the bottom LHS corner. All IC's should now be on the board.

Carefully check you have everything correct. Be sure you have the correct voltage for the CPU. Pop the board into your system and boot up the 80386 monitor with the Z80 "O" command. The monitor should immediately signon. If so you are well on your way to having a fully functional board.

Here is a picture of the board at this stage:-

I have actually added the EEPROM chip. More on this later.

Baby 80486 Debugging
If your board does not signon immediately as described above, don't worry there are a number of things you can do to narrow down the problem.
If you look at the schematic you will see that pin U11A is connected to jumper K101. If this jumper sends a low to U11A pin 1, (a "FORCE_WAIT" signal), it will sent a low to the U110 CPLD pin 15. This sends a permanent low READY to the CPU via this code.

READY = ((!S100_WAIT & BOARD_ACTIVE)
       # (!RAM_CYCLE_WAIT & BOARD_ACTIVE)
       # (!IO_CYCLE_WAIT & BOARD_ACTIVE)
       # (!INTA_CYCLE_WAIT & BOARD_ACTIVE)
       # (!DB_WAIT & LS100_SEL & BOARD_ACTIVE));

What this means it that immediately when the CPU has control of the bus it puts it in a HOLD state. Not even the first opcode cycle is completed. If you have our SMB System Monitor Board you will see the S100 bus address lines held at 0FFFF0H. And the 16 bit data lines at EA34H (the first two bytes of the ROM at FFFF0H).

On the SMB you then set the Switch to "Hold", remove the K101 jumper and toggle the SMB "Single Step" switch. As you do so, the CPU will step forward in the code one word at a time. This is an extremely useful way to debug the hardware. With each step look at the S100 bus lines. For example you can see the mBE0*, mBE1*, mBE2* and mBE3* pulsing low as you step along. BTW, the pattern is not what you might expect, carefully look at the Intel 80486 manual to show how they change for each address. Step the code along to see where the CPU "goes wrong". Examine the hardware around that point.   This approach is your first line of attack. If you don't have a SMB you can rig up a simple "bounce free" switch yourself.

You have other options. The 80386/80486 monitor has at its boot location (FFFF0H) early on code to examine the IOBYTE port (EFH). If it sees bits 7 & 6 low (i.e.. 00xxxxxxB) it will jump to a special "debugging loop" where it will continuously read the value of the IOBYTE and display it on the console. With a value of 00111111B you should continuously see "???????...." on the screen. Changing the IOBYTE bits should correspond to the 7bit ASCII code. This test allows you to check out the read and write 8 bit data buffers (U117 & U116).

You can also opt to run the board in 8 bit only mode, by jumpering K1 (SIXTN*) 1-2.    If you do this you can actually remove U16, U111, U113 and U114 and use only the 8 bit data paths (U116 & U117) on the board. Note the board will run slow. This may be useful with old S100 boards.

Another thing you can do is burn a ROM with just the code B0 33 E6 01 EB FA. This should force the CPU after reset to continuously write "33333..." on the console (assuming its Port 01H).

If all the above fails, try filling the ROM with F4's. When the 80486 has control it should immediately go into a HALT state with the S100 bus line (pin 48) going HIGH. If not, there are probably serious problems with the board.

Remember when we say ROM there are two possibilities. You can use the single ROM on the board (with it's own CPLD code see below) or you can use external ROM on the S100 bus -- typically on our MSDOS Support board. In the case of the latter remember to write even and odd bytes in the two separate ROMs. For beginners for the Baby 80486 board, the onboard ROM is easiest.

Finally there is another way to bypass the ROM entirely. If you have our Z80 board you can write bytes directly in RAM at FFFF0H. To do this you must first remove the MSDOS support board (or inactivate its ROMs). Then with the following Z80 command:-

QO D2,FC                  (Switches RAM at FC000 - FFFFF to RAM at 0H),
S3FF0
B0 33 E6 01 EB FA

Reset then use the "W" command.   Do not use the "O" command, that one modifies RAM if present at 0FFFF0H.
The 80486 should see the above code at FFFF0H and print continuous "3's" on the console.
Be sure the is no ROM at that location in the bus.

BTW, you do not need the MSDOS board ROM for these simple tests. But as soon as you can get it going.

Generally getting the board to signon is fairly straightforward. The hard part is finding it's speed upper limits in your system. In my hands on three different systems here (10, 21 & 21 slots), I found the above settings to be rock solid.   In most cases you can in fact use less wait states and even higher speeds. The Achilles heel for speed is the 8 bit VGA board. High bus speeds are characterized by stray characters appearing on the screen. Without it the board runs fine in most cases at 9MHz. Your mileage of course may vary.    As a side note, I doing a high speed 16 bit Cirrus chip VGA board -- but its a few months off yet.

Baby 80486 Jumper Table
There are less than the usual number jumpers on this CPU board compare to our earlier boards. That said, they need to be set carefully. To run the board as a bus slave (with a Z80 master) with a PHI bus speed of 9.0 MHz (36 MHz Oscillator) here is a typical jumper setup:-

Jumper	Function
JP9	Normally closed. Generate the S100 bus MWRT signal on this board when it is active.
JP8	Normally closed. Generate the S100 bus 2MHz Clock signal on this board when it is active.
K2	2-3, Ignore 80486 Math errors
P8	Normally not used. Used for special "slave of a slave" S100 bus configuration. (See here)
JP12, JP13, JP14	Slave clear, POC & Reset are generated on this board (used only if board is set as a bus master)
P104	pHLDA from S100 bus. For slave configuration 1-2.
JP103	Closed, Pull-up resistor for pHLDA.
K104	HOLD signal to S100 bus. Jumper 1-2.
JP11	Open, pull-up resistor for pHOLD
K101	2-3 (high). If low (1-2) CPU will immediately go to a continuous wait state upon assuming control of the bus. This is used for hardware debugging.
JP19,20 21 & 22	Normally all open unless the board is a bus master.
JP102	Disable PHI input to CPLD. Used during the initial CPLD programming cycle where it is open. Normally closed.
K108	Normally 1-2 for board in Slave mode. 2-3 if bus master.
P103 or P2	CPLD JTAG programming socket for Rockfield Research 1508 programmer. Pin 1 is bottom left.
P11,P12,P14,P101	Wait state jumpers. See the above text.
K5	Unused currently. Available for extra wait states.
TP1	Unused currently. Available as an experimental input to pin 40of the CPLD
K1	Normally 2-3 allows S100 boards to indicate they are capable of accepting 16 bit data. 1-2 force 8 bit mode
RR1 & RR3	In slave mode these pins are NOT connected to a pull-up resistor network. In master mode use 1K pull-ups.
SW1-4	For future modification of the CPLD code. Only SW3 is currently used -- to activate the onboard EEPROM

You can play around with the wait state jumpers. As I said above, if you are not using the VGA board you can often push the CPU to an over 9 MHz S100 PHI clock. After much trial and error what with the VGA board present, I ended up with a Phi of 9 MHz.

BABY 80486 FUTURE MODIFICATIONS
This board is available to numerous modifications of the S100 bus signals. All the critical ones are generated totally within the CPLD. There is a spare "TP1" test pin to jumper your own input to pin 40 of the CPLD. Currently the 4 position dip switch SW1 is also unused and can be used to redirect the CPLD code. There is also a "Diagnostic LED" D5 that can be used to indicate intermediate values within the CPLD code. The latter is very useful.

If you develop useful extensions/modifications please let others in the group know.

Baby 80486 Bugs.
No bugs have been reported for the Baby 80486 board currently. However remember if you are using the onboard port (EDH) to activate the board be sure you jumper P36 1-2 & 3-4. This is because other boards may be expecting the TMA0* line to be low when this board is active.   The onboard port alone will not lower the TMA0* line. I find using the SMB to activate this board to be more reliable for reasons that are not clear to me when using the AMD or DX4 CPU's.

Please remember this board will NOT work the V5.0 or V5.1 16MB Static RAM boards. This is because of an error on those boards where the S100 bus signal SIXTN* was not brought out to the bus via an OC gate. A patch was provided for those boards, but if possible use the newer V6.0a Static RAM board.   All the older S100Computer 4 & 16MB RAM boards work fine. In fact I find that of all our RAM boards, the original 4MB RAM board is best. That one is a real trooper for high speed CPUs!

The 2MHz Oscillator is a little close to the RHS board edge leading to difficulties sliding the card into the S100 slot. Use a socket to hold the chip or use the full length leads on the oscillator so it is well above the board surface. Make sure the oscillator does not touch the pins of U40. Likewise on the LHS for the capacitor C27.

The Silkscreen above P11 should read "RAM_WAIT 1-8" not "RAM_WAIT 1-7"
The Silkscreen for SW3, labeled "Diagnostic_SW1" on the board, should be labeled "Activate ROM".

The original GAL code posted for the VGA Board in the VGA_SEL GAL only decoded the address range A19 - A0. This was fine for the 8088 CPU. However now that we have this board working with the 80486 CPU board we need to decode the full S100 bus range A23 - A0 so the boards ROM and RAM does not appear in every 1MB page when running the CPU in protected mode.   The changes are shown in yellow in the GAL code on this page. The VGA_GAL .ZIP files have also been corrected. If you intend to use this board with any CPU that extends further than 1MB, please correct the VGA board GAL code.

Assembly of the Full Size 80486 Board
Again we will build the board up in functional steps. Please re-read the baby 80486 board assembly before starting here. Most of the steps are the same, however some of the IC numbers and Jumpers are different. We will set the board up configured as an S-100 bus slave. Inputting port 0EDH (in my system, a Z80 monitor "W" or "O" command), will switch in the Full Size 80486 CPU board and switch out the Z80.

This board is our very first 4 layer printed circuit board. Be careful with it. When inserting chips avoid flexing the board by placing it on a flat surface.

Remember there are two ways to activate these slave CPU boards. You can use the onboard GAL0 and input from port 0EDH or you can use our SMB to lower an S100 bus TMA line, by default TMA0*, without even having the GAL0 present. Indeed while not recommended, you can just ground by hand with a jumper pin P2 of P13.

Solder in all the required IC sockets, resistors, resistor arrays, capacitors, jumpers, and the 5V Pololu voltage regulator and if required the 3.3V regulator. Do not add the LED's yet. Be sure you put the resistor arrays in with the correct orientation of pin 1. Check their values before soldering (they are difficult to remove). Remember if you already have 1K pull-up resistors for the S-100 bus vector interrupt lines and DMA lines in your system (for example on your Z80 CPU board), you really don't need the resistors on this board (RR1 & RR3). You can insert single row sockets such as Jameco #78624 in case you want to add pull-up resistors in another system. Be sure and insert the CPU and CPLD socket correctly with the notch at the bottom left-hand corner. You can add the 2MHz Oscillator to P10 now or later. Since it never changes you can solder it in without a socket if you like. Do not add the 40 and 50 pin OTT RAM ribbon cable connector sockets yet.

The Pololu 5 Volt (and if required), 3.3 Volt regulators must not touch the traces under them. Use the straight 5 pin connectors supplied with them. The CPU seems to work fine with the 2.5 Amp regulators, the 5 Amp ones are not required.

For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets. However they are more expensive and you have to be particularly careful not to bend the IC pins. The two clock oscillators can have their own special sockets (e.g. Jameco #133006) but actually I find the "Machine Tooled" IC sockets make a better connection. I in fact solder the 2MHz oscillator directly to the board since it will never be changed.

Next insert all 5 LED's. Before soldering them in place ground the appropriate pin on the U115 socket to make sure it lights up.   I use a blue LED for 80486 active. Unlike the Baby 80486, U115 pins 11 and 9 need to be +5 volts to light up. Install jumper K1 2-3 (assuming a 5V Intel CPU).

Check the voltage to sockets on the board is above 5V by placing the board in your S-100 system using an extender board. With no load you will typically get 5.00V (+/- 0.25V). BTW, your system should boot and run correctly with its Z80 master CPU board. If not, you have a serious solder bridge somewhere on the board. Before you do anything else with a magnifying glass go over every socket on the board and examine for a proper solder joint. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins. Double check.   Extra time here will save you hours later, (Been there, done that! ).

We will next add jumpers and IC's to the board. While on jumpers, please note every time when we talk about jumpers, position 1 is the square pad of the jumper. In order to minimize board trace lengths, its actual position/orientation on the board will differ from jumper to jumper. Sometimes they are top to bottom or left to right, other times the exact opposite. An incorrect jumper can be a real pain in debugging a non-working board. Check with the board schematic each time, to be sure . Make sure you correctly identify pin 2 in each case.

First add the main clock oscillator P5, I generally start with 36MHz but you can use 40MHz if you feel lucky.
Next program the 1508 CPLD (U110). We do this now because we don't want pin I/O conflicts on the bus later. See here for more information on CPLD programming.
The .JED file is provided at the bottom of this page. Here is a picture of the board at this stage.

Next burn the two GAL's using the JED code at the bottom of this page. You can use a Wellon VP290 or similar "Prom Burner".
486_GAL0.JED is for the U101 GAL, 486_GAL1.JED is for the U10 GAL. Both are Lattice 22V10's. See here for more information on GALs.
Please note that while the 486_GAL0 GAL is identical to that of the above Baby 80486 GAL0. The code in the Baby 486_GAL1 is slightly different for the Full Size 80486 Board 486_GAL1. (Its pin 19 goes low for any address above 16MB, i.e., for OTT RAM board addresses).

Add both GALs to the board. Add U109 and U102 and jumper P13 1-2.
Use the Z80 monitor "O" command (input port EDH) and check that the jumper on P13 toggles High->Low--> High...
Add U5, U107, U115, U40 and jumper K108 1-2, K104 1-2 and P104 1-2.

Repeat the "O" command test. The (blue) D1 LED should light up (and probably the S100_SEL*).
In the default configuration downloaded here the CPLD Diagnostic LED should also light up.
Control should NOT return back to the Z80. The system just hangs.

If D1 does not light up, within the CPLD code, below "\* Activate the board....", use the Diagnostic LED to determine where the problem is.

Pinnode = [reg2..0];                    /* Need 3 D type Flip Flops */
reg0.d = TMAx;                          /* TMAx goes low-> high */
reg0.ckmux = !PHI;
reg0.ar = !MASTER_RESET;                /* Return to high on reset */
!HOLD = reg0;                           /* Lower S100 bus HOLD line */

!XFERI = reg0 & pHLDA;                  /* Activate the S100 bus Control lines, when pHLDA comes back */

!DIAG_LED = reg0;                       /* Flag to show progress */

reg1.d = reg0;
reg1.ck = pHLDA;                        /* S100 bus grants bus by raising pHLDA line */
reg1.ar = !reg0;
...
...

Check and be sure pin1 of U2, U3 & U4 goes from High to Low with the "O" command.
Add U2, U3 & U4, repeat the above test.
Repeat the "O" command test. The (blue) D1 LED should light up.

Here is a picture of the board at this stage.

Add U9. Check and be sure pin19 of U6, U7, U8 & U13 is high even with the "O" command.

Add U6, U7, U8 & U13. On power on check that in all cases +/- "O" command pins 1 & 19 of each remain low.
Repeat the "O" command test. The (blue) D1 LED should light up.

Check and be sure pin19 of U111, U112, U1113, U114, U103, U104, U105, & U116 are all high BEFORE the "O" command (i.e. when the Z80 has the bus).
This is essential to make sure these drivers are not driving the data line when the 80486 board is not active. If any are low, determine why.
After the "O" command some may be low, that's OK.

Add U111, U112, U1113, U114, U103, U104, U105, & U116 (a 74LS244).
Repeat the "O" command test. The (blue) D1 LED should light up.

Here is a picture of the board at this stage.

Add U32, U33 and U31.
Repeat the "O" command test. The (blue) D1 LED should light up.
Check Pins 1 & 19 of U32 and U33 go low.

Add Jumper JP8, JP9 (MWRT), K101 2-3, JP17 & K2 2-3 (off) and JP104 (beside the 40MHz oscillator).
It's best if U26 is a 74F14 or 74S14. Finally add P10 the 2 MHz Oscillator.
For now leave unconnected, JP103, K102, JP1, JP2, JP3, JP101, JP15, JP13,JP20, JP19, JP21, JP22, JP16, JP12 and JP14.

Jumper the wait state jumpers as shown here:-



Here is a picture of the board with everything added except the CPU

Next we will add the CPU. BE SURE TO ADD THE 80486 CPU CHIP SO IT IS UPSIDE DOWN ON THE BOARD. Pin 1 it the top RHS corner. Also add jumper K1 (normally 2-3 for a 5V power supply to the CPU). If you have a choice I suggest you first try the board with a cheap/common 80486/DX. Ideally one from a working PC motherboard. If you use a rare/expensive AMD chip or the (even rarer), 80486 DX4. Be absolutely sure the K1 jumper is set for 3.3Volts on its center pin. Measure this to confirm before adding the chip. See the write-up above for adding/removing these chips. The reason for the unusual orientation of the CPU is because we want its 32 data lines to be as short as possible to the OTT32 bit bus connector. i know it does not look pretty.

Carefully check you have everything correct. Be sure you have the correct voltage for the CPU. Pop the board into your system and boot up the 80386 monitor with the Z80 "O" command. The monitor should immediately signon. If so you are well on your way to having a fully functional board.
Finally you can add the OTT Bus connectors and test the board in Real and Protected RAM modes.

Do a "Memory Map" (Using the "A" command in PM). All available RAM should show up as "R"'. If you see an occasional "p" add a wait state to your RAM board. At 10MHz I use two wait state jumpers on the RAM board and for reliability have P11 jumpered 15-16 on this board.

Testing RAM is critical. There is a lot of it and even at these speeds a complete test of 32 MG takes over two hours. Test a small amount of RAM first to save time using the "7" menu option. Say 2000000 to 200FFFF. The test writes bytes, words and double words into RAM checking all the time writes did not change other areas of RAM. These are launched from the 80386 Protected Mode "K" menu using the "J" command.
Here is the menu:-

The "T" menu option is also important. The "T" routine relocates a small executable routine loop into PM mode RAM on the S100-OTT board and jumps to that routine. It simply outputs a character on the console. But is doing so rapidly and continuously flips back and forth between the S100 Bus (for I/O) and the S100-OTT bus. This is a crucial and difficult test for the board because it is rapidly switching the CPU clock frequencies.

If your board passes these RAM tests you now have a fully functional board. Congratulations -- enjoy 80486 PM programming on the S100 bus.

Here is a picture of the board at this final stage:-

OTT RAM Cables
The Full Size 80486 board requires two ribbon cable connectors to the OTT RAM board. It is essential that these cables be made up properly. There is a special crimp tool to attach ribbon cables to connectors. See the picture below. Alternatively it can be done in a vice. It's important that the cable be aligned properly before pressing the top down evenly on to the bottom of the socket. The length of the cable should bridge between two S100 slots. For debugging and ease of removal I also use a longer cable (see below). You can even use 10" cables to place the CPU in an extender board -- though this usually means you have to reduce the clock frequency.

Be sure and get board sockets that have ejectors built in as the cable connections will weaken if you pull out the socket by the cable. Also, be absolutely sure that pin 1 of each socket (normally the red wire on a ribbon cable), is connected to pin 1 on the other socket. Many sockets have the pin 1 location marked with an arrow. Sockets often have a notch in the middle of the front surface, this must aligned with the corresponding area of the board socket. Check everything carefully before you crimp the cable.

Theory Of Operation for the Full Size 80486 CPU Board
In Real Mode the Full Size CPU board works almost the same as for the Baby CPU board. The CPLD code is almost (but not exactly) the same.   The key difference between the two boards is the 32 data lines coming from the CPU. On the Baby CPU board they are just buffered and sent to the S100 bus. On the Full Size there is a gate for each line which redirects the data line to the S100 bus or (if the address is above 16MB) to the OTT bus connector (P9) at the top of the board. The actual CPU data lines are directly connected to the OTT connector P9.

The signal S100_Sel* feeds a 74S32 which activates the S100 bus data lines for any RAM addresses below 16MB (and all I/O and interrupts). Here is the relevant circuit:-

You may also notice in the schematic that I managed to combine the S100 bus 8 bit Data out buffer from the CPU (U117 on the Baby 80486 board) with the lower 16 bit data buffer (U114) in the CPLD code. This saves one 74LS244 IC on the board. It should in fact be possible to shrink the five S100 bus 74LS245 buffers down to two buffers in the CPLD, however the code really gets complex. I opted for the simple hardware approach.

Full Size 80486 Jumper Table
There are less than the usual number jumpers on this CPU board compare to our earlier boards. That said, they need to be set carefully. To run the board as a bus slave (with a Z80 master) with a PHI bus speed of 10.0 MHz (40 MHz Oscillator) here is a typical jumper setup:-

Jumper	Function
JP9	Normally closed. Generate the S100 bus MWRT signal on this board when it is active.
JP8	Normally closed. Generate the S100 bus 2MHz Clock signal on this board when it is active.
K2	2-3, Ignore 80486 Math errors
JP12, JP13, JP14	Slave clear, POC & Reset are generated on this board (used only if board is set as a bus master)
P104	pHLDA from S100 bus. For slave configuration 1-2.
JP103	Open, Pull-up resistor for pHLDA.
K104	HOLD signal to S100 bus. Jumper 1-2.
JP101	Open, pull-up resistor for pHOLD
K101	2-3 (high). If low (1-2) CPU will immediately go to a continuous wait state upon assuming control of the bus. This is used for hardware debugging.
JP19,20 21 & 22	Normally all open unless the board is a bus master.
K108	Normally 1-2 for board in Slave mode. 2-3 if bus master.
P103 or P2	CPLD JTAG programming socket for Rockfield Research 1508 programmer. Pin 1 is bottom left.
P11,P12,P14,P101	Wait state jumpers. See the above text.
K4	Unused currently. Available for extra wait states.
JP104	Normally 2-3 allows S100 boards to indicate they are capable of accepting 16 bit data. 1-2 force 8 bit mode
RR1 & RR3	In slave mode these pins are NOT connected to a pull-up resistor network. In master mode use 1K pull-ups.

You can play around with the wait state jumpers. Even if you are not using the VGA board you can often push the CPU to a 10 -12MHz S100 PHI clock.

Full Size 80486 Bugs & Notes.
No bugs have been reported for the Full Size 80486 board currently. Again remember if you are using the onboard port (EDH) to activate the board be sure you jumper P36 1-2 & 3-4. This is because other boards may be expecting the TMA0* line to be low when this board is active.   The onboard port alone will not lower the TMA0* line.

Also please remember this board will NOT work the V5.0 or V5.1 16MB Static RAM boards. This is because of an error on those boards where the S100 bus signal SIXTN* was not brought out to the bus via an OC gate. A patch was provided for those boards, but if possible use the newer V6.0a Static RAM board.   All the older S100Computer 4 & 16MB RAM boards work fine. In fact I find that of all our RAM boards, the original 4MB RAM board is best. That one is a real trooper for high speed CPUs!

To access the PM RAM on our OTT RAM board(s) its absolutely essential that U26 on the 80486 board be a 74F04. Its also essential that the corresponding chip on the V2 OTT RAM board (U17) be a 74S04. With this setup a 24MHz CPU clock (using a 48 MHz Oscillator) works fine in PM.

This CPU board was built for speed. A full day was spent hand re-doing some of the Freerouter/KiCAD routes, (which itself took 3 days to complete). Some lines like the critical CPU WR* pWR, pDBIN etc. lines are laid down with direct and wide traces. The copper on the board is 2X that of our "normal" boards.    If you wish to run this board with an S100 bus Phi clock of say 8MHz, more or less any good quality 74LSxxx chips will be fine.

For high speed however you have to tweak the buffers.
Besides the 74F04 for U26, you will need 74F245's for U105, U104, U103, U112, U111, U113 and U114.   Also a 74F244 for U116.
The address line buffers U2, U3 & U4 should be 74F373's
Use also a 74F244 for U32 and a 74F240 for U33.
For reasons I don't understand U8, U13, U6 and U7 must remain 74LS245's. However the OR gate U9, should be a 74S32.

Getting the right settings for the Full Size 80486 to work with OTT RAM requires a bit of playing around with the wait state jumpers on this board and the wait state jumpers on the OTT RAM board. To my surprise I found in fact the board works best with OTT RAM at high Phi speeds.   Currently my best setting is:-
P5 = 48MHz Oscillator. No wait states on the V2 OTT RAM board, and P11 jumpered 15-16, P14 5-6, P12 9-10 and P101 5-6 using an Intel 80486 DX2 or DX4 chip.

The high speed Phi clock is surprising. However both my 10 slot and 21 slot motherboards seem to work fine with a Phi of 12MHz with the full size board. The RAM chips are CY62167ELL-45 either soldered directly to the board or on our V06d Mezzanine boards.

Finally when you arrive at a good setting, use the PM "Y" command to check the 80486 can execute code in your OTT RAM.

The Achilles heal of the board seems to be the U9-U7 buffers (and U26). At one point I thought the CPU WR* signal may be too weak to drive all these buffers and split it up into 4 separate lines (with a 74LS125). This was a total disaster. WR* needs to very quickly get to these buffers!

With good quality (Ti/Mouser) chips with the above modifications the board is rock solid with the above wait states. However to be sure your system is reliable run the monitor protected mode "Y" and "J" commands, ideally overnight on S100 and OTT RAM in your system.

Here is a short video showing the RAM tests in action.
Note this video will take time to upload/buffer when it is first run. Please wait.



I have just completed testing of a new (4 layer) V3 32/64MB OTT Static RAM board which I highly recommend for use with this CPU board (and the earlier 80386 CPU board). If you intend to initially use the V2 OTT RAM board (it works fine at 24MHz), use the mezzanine chip arrangement on that board. Later you can just transfer the (expensive) RAM chips to the V3 board. Please see here for more information about the V3 OTT 32/64MB RAM Board

Here is a picture of the optimum 80486/16MB S100/32MB OTT RAM board combination:-

Baby & Full Size 80486 Board Parts.
The CPLD is from Mouser, Part # 556-ATF-1508AS-10JU84. Rick Bromagem has provided a BOM for the baby and full size 80486 Boards at the bottom of this page. For the 80486 (or 80486 DX/2 etc.) it probably the easiest to buy a 80486 motherboard on eBay, check that it signs on and then pull the chip.
I also managed to find on eBay a DX4 and AMD Am5x86-P75 chip. This chip requires a 3.3V power supply (as well as the Pololu 5V board supply). So you need to add the Pololu 3.3V regulator and be absolutely sure you jumper K3 for 3.3 volts and not 5 volts. The board seems to work the same with both CPU's. I did not notice a very significant speed improvement with the AMD chip. At these speeds none of the CPU's need a heat sink.   Be sure and get a 168 pin CPU socket with a clear area in its center. I obtain these (and many other components used here), from Anchor Electronics and Jameco.

The best CPU by far is the Intel 80486-DX4 chip. This chip has a 3X internal clock speed. However it too requires a 3.3V power supply. If you use it, be absolutely sure you have K1 jumper set to 3.3 volts. These chips however are rare.

Full Size 80486 Bugs & Notes.
No bugs have been reported for the Full Size 80486 board currently. Again remember if you are using the onboard port (EDH) to activate the board be sure you jumper P36 1-2 & 3-4. This is because other boards may be expecting the TMA0* line to be low when this board is active.   The onboard port alone will not lower the TMA0* line.

Also please remember this board will NOT work the V5.0 or V5.1 16MB Static RAM boards. This is because of an error on those boards where the S100 bus signal SIXTN* was not brought out to the bus via an OC gate. A patch was provided for those boards, but if possible use the newer V6.0a Static RAM board.   All the older S100Computer 4 & 16MB RAM boards work fine. In fact I find that of all our RAM boards, the original 4MB RAM board is best. That one is a real trooper for high speed CPUs!

To access the PM RAM on our OTT RAM board(s) its absolutely essential that U26 on the 80486 board be a 74F04. Its also essential that the corresponding chip on the V2 OTT RAM board (U17) be a 74S04. With this setup a 24MHz CPU clock (using a 48 MHz Oscillator) works fine in PM.

This CPU board was built for speed. A full day was spent hand re-doing some of the Freerouter/KiCAD routes, (which itself took 3 days to complete). Some lines like the critical CPU WR* pWR, pDBIN etc. lines are laid down with direct and wide traces. The copper on the board is 2X that of our "normal" boards.    If you wish to run this board with an S100 bus Phi clock of say 8MHz, more or less any good quality 74LSxxx chips will be fine.

For high speed however you have to tweak the buffers.
Besides the 74F04 for U26, you will need 74F245's for U105, U104, U103, U112, U111, U113 and U114.   Also a 74F244 for U116.
The address line buffers U2, U3 & U4 should be 74F373's
Use also a 74F244 for U32 and a 74F240 for U33.
For reasons I don't understand U8, U13, U6 and U7 must remain 74LS245's. However the OR gate U9, should be a 74S32.

Getting the right settings for the Full Size 80486 to work with OTT RAM requires a bit of playing around with the wait state jumpers on this board and the wait state jumpers on the OTT RAM board. To my surprise I found in fact the board works best with OTT RAM at high Phi speeds.   Currently my best setting is:-
P5 = 48MHz Oscillator. No wait states on the V2 OTT RAM board, and P11 jumpered 15-16, P14 5-6, P12 9-10 and P101 5-6 using an Intel 80486 DX2 or DX4 chip.

The high speed Phi clock is surprising. However both my 10 slot and 21 slot motherboards seem to work fine with a Phi of 12MHz with the full size board. The RAM chips are CY62167ELL-45 either soldered directly to the board or on our V06d Mezzanine boards.

Finally when you arrive at a good setting, use the PM "Y" command to check the 80486 can execute code in your OTT RAM.

The Achilles heal of the board seems to be the U9-U7 buffers (and U26). At one point I thought the CPU WR* signal may be too weak to drive all these buffers and split it up into 4 separate lines (with a 74LS125). This was a total disaster. WR* needs to very quickly get to these buffers!

With good quality (Ti/Mouser) chips with the above modifications the board is rock solid with the above wait states. However to be sure your system is reliable run the monitor protected mode "Y" and "J" commands, ideally overnight on S100 and OTT RAM in your system.

Here is a short video showing the RAM tests in action.
Note this video will take time to upload/buffer when it is first run. Please wait.



I have just completed testing of a new (4 layer) V3 32/64MB OTT Static RAM board which I highly recommend for use with this CPU board (and the earlier 80386 CPU board). If you intend to initially use the V2 OTT RAM board (it works fine at 24MHz), use the mezzanine chip arrangement on that board. Later you can just transfer the (expensive) RAM chips to the V3 board. Please see here for more information about the V3 OTT 32/64MB RAM Board


Baby & Full Size 80486 Board Parts.
The CPLD is from Mouser, Part # 556-ATF-1508AS-10JU84. Rick Bromagem has provided a BOM for the baby and full size 80486 Boards at the bottom of this page. For the 80486 (or 80486 DX/2 etc.) it probably the easiest to buy a 80486 motherboard on eBay, check that it signs on and then pull the chip.
I also managed to find on eBay a DX4 and AMD Am5x86-P75 chip. This chip requires a 3.3V power supply (as well as the Pololu 5V board supply). So you need to add the Pololu 3.3V regulator and be absolutely sure you jumper K3 for 3.3 volts and not 5 volts. The board seems to work the same with both CPU's. I did not notice a very significant speed improvement with the AMD chip. At these speeds none of the CPU's need a heat sink.   Be sure and get a 168 pin CPU socket with a clear area in its center. I obtain these (and many other components used here), from Anchor Electronics and Jameco.

The best CPU by far is the Intel 80486-DX4 chip. This chip has a 3X internal clock speed. However it too requires a 3.3V power supply. If you use it, be absolutely sure you have K1 jumper set to 3.3 volts. These chips however are rare.

The 80486 Board as a Bus Master
This board will normally be used by most user as a bus slave. See here for more details about S100 bus master & slave boards. If you wish this board to boot up immediately upon power on as a "Bus Master" the CPLD code needs to be changed. If it is the only CPU in your system and you don't need it to call a slave CPU board or disk controller the CPLD code is actually quite simple, but to allow it as a master to call up a slave you need the following. We will us our 68030 Slave board as a test case. First confirm it works with your Z80 CPU (master).
Then "burn" in the CPLD code provided in the file M485_MASTER.ZIP at the bottom of this page. The relevant changes to the normal slave mode file are:-

Pinnode = [reg2..0];

RESET_80486 = !MASTER_RESET;
BOARD_ACTIVE = MASTER_RESET;       /* Active high */

reg0.d = !HOLD;                    /* HOLD will be HIGH, unless a slave requests the bus then its HIGH -> LOW */
reg0.ckmux = !PHI;
reg0.ar = !MASTER_RESET;
CPU_HOLD = reg0;                   /* Set CPU_HOLD HIGH to stop the 80486 CPU */

reg1.d = CPU_HOLDA;                /* CPU_HOLDA back from 80486 returns HIGH when it's ready to grant the bus */
reg1.ckmux = PHI;
reg1.ar = !MASTER_RESET;
pHLDA = reg1;                      /* Let the S100 bus know it received the request, LOW-> HIGH */

XFERII = reg1;                     /* LOW = active */

reg2.d = reg1;                     /* XFERI one clock cycle later */
reg2.ckmux = PHI;
reg2.ar = !MASTER_RESET;

XFERI = reg1;

DIAG_LED = reg1;

INACTIVATE_DATA_LINES = !XFERII;    /* First disable the Address, data and status lines. CTL lines are still enabled */
                                    /* On the slave they are still inactive but the slave CTL lines are now active as well. */
                                    /* i.e.. both CPU's are (for one clock cycle) are driving the CTL lines */

INACTIVATE_CONTROL_LINES = !XFERI; /* Finally disable the master control line and activate the slave address, data and status lines */
                                    /* At this point no master S100 bus lines should be driving the bus. The slave has complete control, PHI included! */

The TMA jumper on P13 should be removed, and the Reset an POC jumpers JP14 and JP12 inserted. The jumpers JP20, JP19, JP21, and JP22 are added to activate the slave Address, data, status and control lines.
To be safe add pull-ups JP102 and JP101. Jumper P104 3-4. Jumper K104 2-3.

Here is a picture of the board configured for Master Mode (with no slaves).
The MASTER MODE CPLD code is provided below.
Remove the Z80 master board from your system and insert this board.

Insert the 68030 slave CPU board exactly as you have used it with your Z80 CPU master. Make sure it is configured to recognize TMA#1. The "B" command in the Z80 monitor.
Our 80486 monitor currently does not have a menu command to activate the TMA#0-3 lines.   We activate TMA#1 using the GAL on the 68030 slave board by:-

QOEEH,02

from the 80486 monitor. The 68030 should signs as shown here. It now controls the S100 bus. The 80486 acts as if it is no longer in the bus!

Exactly the same configuration can be utilized to bring up our 80286 slave CPU board, except this time we utilize TMA#0. Se we output:-

QOEE,01

Here is a picture of the signon:-

Master Mode 2

For those that have time to go further..
The Power on reset does not reliably bring up the 80486. You sometimes need to follow power on with the reset button.
There is an input pin jumper K102 that can be used to have the CPLD code decide -- on the fly decide whether the board is a bus master or slave.
Because the 80486 utilizes ROMS on the MSDOS support board, timer and keyboard interrupts need to be taken care of on any slave CPU board.
Our 8086, 8088 and 68K slave CPU boards currently hang during the above master to slave transition. Something is still not quite right!

In all cases so far I cannot get any of the slave boards to boot CPM or MSDOS. They work fine with the "normal" Z80 master. Seems to give random IDE board errors when control to the slave comes from the 80486. This suggests that somehow the 80486 has not completely let go the bus!!!

An 80386/80486 ROM MONITOR
Both 80486 boards work fine with our "standard" 8086 and 80386 ROM based monitors. To really enjoy working with the 80486 you need to be able to utilize the 32 bit capability of the chip. See 80386 Monitor for a complete description of this process. From there you can download of the 80386 ROM based monitor for the above board. With this monitor in protected mode you can display all the CPU's registers, single step, check interrupts (soft, and in hardware) and examine RAM anywhere in its 4GB address space etc.

NOTES
Some people have had CPU master/slave switching problems with this board. Peter Higgins has writted up a nice summary of the problem.

Problem 1 – Master/slave switching when performed by input from port EDh.

This option has been implemented on all slave CPUs using a GAL or CPLD with inputs obtained directly from the S100 bus. The trigger to enable (and disable) the slave CPU is simply an INPUT to port EDh, allowing master/slave switching under software control without the need for a System Monitor Board. Some of John Monahan’s older software (specifically, CPM86+) also depends on this method to switch in the x86 slave processor.

The problem I encountered was that the switching circuit was being triggered randomly while running either CPM3 on the Z80, or MSDOS on the 80486. This “random trigger” issue was previously mentioned by Jay Jaeger when he encountered it on the S100 PDP-11 board, where the required logic is implemented within one of the board’s CPLDs:

https://groups.google.com/g/s100computers/c/afLCbpQG1B4/m/VeqL7SXlCwAJ

It seems this switching logic is very sensitive to noise on the S100 bus – in my case, the problem went away when I removed an S100 extender board that had been plugged into the last slot of the backplane.

Problem 2 – Master/slave switching when performed by lowering TMA0-3 using the System Monitor Board

The problem I encountered was that when master/slave switching was performed under software control using the SMB, all four of the TMA lines would become active at the same time even though the data output to port EEh was to to lower only TMA0. When performed manually (from the Z80 system monitor) the circuit always performed correctly. This issue has been previously described here by Gary Milliorn when using the 68030 CPU, and by Michael Wachur who presented a detailed analysis of the cause of this problem when using the 80486 CPU:

https://groups.google.com/g/s100computers/c/nqoK8Q3Hyk4/m/fx85IhDRGAAJ

https://groups.google.com/g/s100computers/c/iBmkGTRDi_Y/m/_lk8Kvm3AAAJ

The cause is related the design of the SMB, which latches its address lines to improve the appearance of its hex displays. When the SMB is used with very fast CPUs the latched address provided to the address decoder for the TMA port select circuitry is that of the previous bus cycle – resulting in incorrect data being saved into the register storing the bits controlling the four TMA lines. Gary and Michael solved the problem (using different methods) by delaying the slave CPU generation of the bus write control signal. I decided not to mess with the 80486 or 68030 boards, and instead opted to “fix” the design of the SMB. I replaced the SMB’s LS273 address latches with LS373s that have their control inputs jumpered so the LS373s simply function in “data pass through” mode. This completely solves the problem with the TMA select logic, and avoids the potentially disastrous consequences of having the bus master and all slave boards going active simultaneously.

A Production S-100 Board.
Realizing that a number of people might want to utilize a board like this together with a group of people on the Google Groups S100Computers Forum, "group purchases" are made from time to time. Please see here for more information.

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